The Road Safety Ideathon at PDEU, jointly supported by IEEE Intelligent Transportation Systems Society (ITSS), IEEE Gujarat Section, and Innovation and Incubation Cell (IIC) PDEU. The ideathon is scheduled for 27–28 September 2025. · Day 1 (27 Sept): Keynote talks and panel discussions with experts from Government, Industry, and Academia. · Day 2 (28 Sept): Final ideathon presentations, poster session, and prize distribution. Funding & Support: · IEEE ITSS has extended support of USD 1000. · IEEE Gujarat Section is contributing ₹10,000. · IIC PDEU will fund prototype development for all winning teams and provide honorarium support to experts. Prizes: · 1st Prize: ₹15,000 · 2nd Prize: ₹10,000 · 3rd Prize: ₹5,000 Additionally, all winning teams will receive prototype development support from IIC PDEU. PDEU , Gandhinagar, Gujarat, India, 382009

Key discussion points: · Gathering material and systematic note-taking. · Avoiding plagiarism through proper citation. · Understanding types of sources (peer-reviewed, scholarly, referred). · Structuring the research paper (Title, Abstract, Introduction, Related Work, Problem Formulation, Proposed Work, Experiments, Results, and Conclusion). · Writing an effective Introduction, contributions, and organization of the paper. · Importance of diagrams, pseudocode, and flowcharts in proposed work. · Presenting results with proper analysis and comparisons. Agenda: Key takeaways of the session: · Learned strategies for efficient note-taking and literature organization. · Understood plagiarism, its consequences, and methods to avoid it. · Gained knowledge of credible sources and their importance. · Acquired skills to write structured sections of a paper systematically. · Understood how to frame problem statements and proposed work clearly. · Learned to support experiments with proper diagrams, pseudocode, and analysis. · Developed awareness of academic writing standards for paper acceptance. Room: 501, Bldg: N block, Nirma University, SG Highway, Ahmedabad, Gujarat, India, 382481

iChip 3.0 is a 7-hour FPGA Innovation Hackathon designed to challenge participants’ skills in Verilog coding, debugging, and digital circuit design. Organized under CASS Convergence 2025, this event provides a hands-on platform for students to explore the journey from code to chip implementation. Participants will debug, design, and deploy digital circuits on FPGA boards, competing in multiple challenge rounds. The hackathon not only tests technical knowledge but also encourages teamwork, creativity, and time-bound problem-solving. With limited registrations on a first-come, first-serve basis, the event promises intense competition, innovation, and exciting prizes for winners. Co-sponsored by: Charotar University of Science and Technology (CHARUSAT) Room: Project Lab 2, EC Dept., A6 Building, CSPIT, Bldg: A6, Department of Electronics and Communication, Charotar University of Science and Technology (CHARUSAT), CSPIT Campus, Off Nadiad-Petlad Highway, Changa, Anand, Gujarat, India, 388421